Method of making semi-conductor devices with plated area



May 31, 1966 P. R. LEVI-LAMOND 3,253,320

METHOD OF MAKING SEMI-CONDUCTOR DEVICES WITH PLATED AREA Original FiledFeb. 25, 1959 FIG. I

e/ C I FIG. 2

' FIG. 2a ELECTROLESS PLATED NICKEL C B E 2b '.,I bv\ I NICKEL I NICKELELECTROLESS PLATED 0N l5 ll I2 ELECTROLESS PLATED on AND SINTERED TO ANDSINTERED T0 SEMICONDUCTOR SEMICONDUCTOR INVENTOR. PIERRE R. LEVl LAMONDATTORNEY S United States Patent 7 Claims. (Cl. 29-255 This applicationis a division of copending application Serial Number 795,517, filedFebruary 25, 1959.

The present invention relates in general to junction bar transistors andmore particularly concerns a novel transistor of this type characterisedby sturdy construction and exceptionally low bulk collector resistance.Moreover, the novel techniques for fabricating this transistorsimplifies its assembly while facilitating the production of a largenumber of individual bar transistors having uniform electricalcharacteristics.

The importance of lowering bulk collector resistance will be betterunderstood by first considering some basic physical principlesapplicableto a junction transistor and the usual physical construction of apractical bar junction transistor. In a conventional bar transistor, avery narrow base region separates much wider emitter and collectorregions of opposite conductivity types so that oppositely polarized P-Njunctions are formed between the base and each of the latter regions.Normally, a rod at each end of the bar is alloyed thereto to support thebar above a suitable supporting base and serve as electrical connectionsto the emitter and collector regions. A third lead is directly connectedto the narrow base region. As a result, virtually the entire resistanceof the relatively Wide collector region is presented between the baseand collector electrodes.

While this resistance, called the bulk collector resistance, is notobjectionable for low frequency operation, its presence is extremelydetrimental to high frequency operation because the effective capacityacross the normally reverse-biased junction between base and collectormust exchange charge with an external circuit through the bulk collectorresistance. A capacity is established across the junction by theoppositely polarized charge layers which accumulate 011 opposite sidesof the junction. The spacing between these charge layers is inverselyproportional to the magnitude of the reverse biasing potential. Sincecapacity is inversely proportional to the spacing between opposed chargelayers, it follows that at low reverse biasing potentials, this capacityis not insignificant and the time constant of such capacity in serieswith the bulk collector resistance may be sulficiently high to seriouslyimpair high frequency operation.

One approach to solving this problem is disclosed in Patent Number2,866,140. Bulk collector resistance is reduced by connecting a leadfrom a point in the collector region spaced from but near the baseregion to the collector lead. While this technique does lower the bulkcollector resistance, it has a number of disadvantages. The connectinglead is fragile and difficult to attach between the desired point in thecollector region and the collector lead. Furthermore, this connectionmust be made to each bar individually. Moreover, it is difiicult toprecisely locate the point of connection near the base region in such amanner that the electrical characteristics of transistors produced in abatch remain substantially the same.

Accordingly, the present invention contemplates and has as an importantobject, the provision of a. junction bar transistor of simple and sturdyconstruction characterised by a relatively low bulk collector resistancewhich may 3,2533% Patented May 31, 1966 be reproduced from unit to unitwithin relatively close tolerances.

It is another object of the invention to provide a method forfabricating junction bar transistors in accordance with the precedingobject with relatively few easily controlled steps so that a largenumber of individual transistors may be rapidly fabricated to havenearly uniform electrical characteristics.

According to the invention, the novel transistor is a bar ofsemiconductor material having two closely spaced oppositely polarizedrectifying junctions defining a base region which separates a collectorregion from the emitter region. At least one of the regions separated bythe base region includes a layer of conducting material deposited on aface thereof and extending close to but spaced from the base region. Anelectrode is connected to the conducting layer. Preferably, thiselectrode also serves as the mechanical support for the bar. In apreferred form of the invention, both collector and emitter layersinclude this conducting layer and attached electrode.

According to the method for fabricating the novel transistor, a crystalslice having rectifying junctions is prepared in a conventional manner.Exposed faces of the slice including the base region and thinimmediately adjacent strips of the collector and emitter regions aremasked with acid resistant material. The unmasked surfaces of thecrystal slice are then plated with conducting material. The platedcrystal slice is cut across the junctions into bars and secured to rigidconducting support members near the ends of the bars to providemechanical support and an electrical connection to the emitter andcollector regions.

Other features, objects and advantages of the invention will becomeapparent from thefollowing specification when read in connection withthe accompanying drawing in which:

FIG. 1 is a perspective view of a bar transistor according to theinvention; and,

FIG. 2 is a perspective view of a crystal slice after being plated butbefore being cut into individual bars with FIGS. 2a and 2b showingenlarged views of the encircled corners 2a and 2b, respectively, showingthe different layers of materials.

With reference to the drawing, and more particularly FIG. 1, thereof, aperspective view of the novel bar transistor is shown.

The base region 11 of the bar 10 separates the emitter region 12 fromthe collector region 13. P-N junctions l4 and 15 of opposite polarityseparate the base region 11 from emitter l2 and collector 13,respectively.

A conducting layer 16 is deposited upon the face 21 of collector 13. Thelayer 16 covers nearly the entire area of the face 17 and ends veryclose to, but spaced from the base region 11.

A similar conducting layer 18 covers most of the area of the face 21 ofemitter region 12. Conducting rods 22 and 23 are mechanically andelectrically connected to layers 18 and 16, respectively, to provide asupport for the entire bar upon a suitable base (not shown) and anelectrical connection to the respective regions. A third rigidconducting rod 24- is on the far side of the bar, preferably in abuttingrelationship therewith but electrically insulated therefrom. A lead 25is connected between the rod 2 and the base region ll.

This arrangement of rods thus provides a sturdy support for the bar andadditionally serve as electrical connections to the emitter, base andcollector. The close proximity of the layer 16 to the base region 11minimizes the effective bulk collector resistance between the base andthe collector electrode 23. Moreover, the relatively large area ofcontact means that the precise spacing between the junction 15 and theleft edge of the layer 16 is not especially critical for obtaining adesired value of bulk collector resistance. Furthermore, the simple formof the layer 16 facilitates duplicating this spacing when it is desiredto produce a large number of units having like electricalcharacteristics. Still another advantage is that the layers 16 and 18form convenient locations for securely connecting the electrodes 22 and23 to insure a good mechanical and electrical connection.

Referring to FIG. 2, there is illustrated a perspective view of acrystal having two closely spaced grown junctions 14 and 15 and theconducting layers 16 and 18 deposited upon the faces 17 and 21,respectively. Reference to this drawing will be helpful in understandingthe method of fabricating the bar transistor shown in FIG. 1. Thecrystal slice 26 is cut from a crystal which may be grown by any one ofthe well-known techniques to provide the base region 11 separating theemitter region 12 from the collector region 13. The slice is firstcleaned with a degreasing agent and then stained by a preferential etchso that the base region is clearly distinguishable from the emitter andcollector regions.

The entire exposed surfaces of the bracketed section 27, which includesthe exposed surfaces of the base region 11 and the immediately adjacentareas in emitter region 12 and collector region 13, are masked withsilicone tape, varnish, polystyrene, wax, or other suitable acidresistant materials. The masked crystal slice is then dipped into asolution of electroless nickel at a temperature of approximately 90 C.for about five minutes to plate the unmasked surfaces with a layer ofnickel. A temperature range of 75 C. to 110 C. and a time range of from2 to minutes have been employed with satisfactory results. A longer timeresults in increased amounts of nickel being deposited upon the crystalslice. However, if allowed to remain in the solution too long, peelingWlil result. By way of example, a suitable electroless nickel bathincludes the following compounds in the indicated densities.

An alkali for neutralizing, such as NH OH, is added to bring the pHwithin the range of 8 to 10.

The mask is then removed and the deposited layer of nickel sintered intothe crystal by heating the plated crystal in vacuum for ten (10) minutesat substantially 800 degrees centigrade plus or minus 50 degrees.

A thin layer of nickel oxide forms. A layer of noble metal will notadhere to the nickel oxide. To prepare a surface to which a noble metalwill adhere, the exposed areas 27 are again masked with acid resistantmaterial and the unmasked surfaces again electroless nickel plated inthe manner described above. This second layer of nickel is then platedwith gold by immersion or electroplating. Alternatively, it may beplatedwith platinum by electroplating. The mask is then removed and thelayers 16 and 18, as shown in FIG. 2, are securely electrically andmechanically connected to the emitter and base regions 12 and 13,respectively. The steps of plating and sintering insure a goodmechanical and electrical connection to the semiconducting regions whilethe second nickel plating followed by noble metal plating insures a goodohmic contact to the first layer of nickel.

The structure of FIG. 2 is then cut in a direction normal to thejunctions 14 and 15 to produce the bars like that shown in FIG. 1.Layers 18 and 16 are secured to rods 22 and 23, respectively, bywelding, soldering, alloying or other suitable means which insures asecure mechanical and electrical connection. The members 22 and 23reside in a conventional supporting base (not shown). This base alsoincludes member 24 which presses against the bar to help hold itsecurely in place. Finally, the lead 25 is connected from the baseregion 11 to the contime.

ducting rod 24 and the entire unit encapsulated to complete thestructure.

The novel methods thus permit the fabrication of a large number oftransistors with a relatively few number of steps in a manner whichenables relatively unskilled personnel to produce units havingexceptionally good mechanical and electrical characteristics in arelatively short The importance of the relative simplicity of the novelmethod is better appreciated when the small size of the bar isconsidered. A typical value for the thickness of the crystal slice is0.01 inch. A typical width of the base region is 0.0001 inch. A typicalvalue for the length of the bar shown in FIG. 1 is 0.200 inch.

A transistor constructed in accordance with these techniques made ofsilicon having a resistivity of 2.5 ohms/ centimeter showed an averagebulk collector resistance of 75 ohms. This compared with a bulkcollector resistance of 250 ohms for a comparable bar transistor notincluding the conducting layers. Moreover, it is relatively easy toduplicate these characteristics from unit to unit because the edge ofthe layer facing the base region 11 is relatively large so that thedistance between this edge and the junction 15 may deviate somewhat froma desired nominal value to achieve a desired bulk collector resistance.Despite this tolerance, the novel methods of fabrication facilitatemaintaining this spacing within very close tolerances so that inproduction the low bulk collector resistance has been regularlymaintained within 10 ohms of the nominal 75 ohm value.

The specific times, temperatures and materials disclosed herein are forillustrating the best mode now contemplated for practicing theinvention. It is evident that those skilled in the art may now makenumerous modifications of and departures from the specific examplesdescribed herein without departing from the inventive concepts.Consequently, the invention is to be construed as limited only by thespirit and scope of the appended claims.

What is claimed is:

1. A method of making semi-conductor devices including the steps ofmasking the exposed surfaces of the base layer of one conductivity type,separating two rectifying junctions, and the exposed areas, marginallyadjacent to said rectifying junctions, of the opposite conductivitytype,

to said base layer, said layers being in a semiconductor crystal slice,plating the unmasked areas, and cutting said crystal across saidjunctions.

2. A method of making semi-conductor devices including the steps ofmasking the exposed surfaces of the base layer of one conductivity type,separating two rectifying junctions, and the exposed areas, marginallyadjacent to said rectifying junctions, of the opposite conductivitytype, to said base layer with acid resistant material, said layers beingin a semiconductor crystal, electroless nickel plating said maskedcrystal, removing said mask, sintering said plated nickel into thecontacting surfaces of said crystal, again masking said exposed surfacesand areas with acid resistant material, electroless nickel plating saidcrystal masked the second time, and plating said crystal masked thesecond time with a noble metal.

3. A method in accordance with claim 2 wherein said noble metal is fromthe group of gold and platinum.

4. A method in accordance with claim 2 wherein said sintering step iscarried out in a vacuum at a temperature of substantially 800 degreescentigrade for substantially ten minutes.

5. A method in accordance with claim 2 and further including the stepsof removing said mask, slicing said crystal across said junctions toform bars having conductively plated surfaces spaced from said baseregion on opposite sides thereof, and welding rigid conductingsupporting members to said conductively plated surfaces.

6. A method of establishing ohmic contact with a semiconducting regionincluding, electroless nickel plating said semiconducting region in aplating bath, removing said 5 6 semiconducting region from said platingbath and imme- 2,937,692 5/1960 Kitchens et a1. 148-33.3 diatelyinserting said region, While still wetted by said plat- 2,957,112 10/1960 Sils 317-234 ing bath, into a vacuum furnace and heating for asufli- 3,104,991 9/1963 MacDonald 14833.3 XR cient length of time at 800C. to provide an exposed sur- OTHER REFERENCES face of nickel oxide andelectroless nickel plating the latter 5 surface to provide an exposedsurface of nickel. A Dlctlonary of Metallurgy y Mel'llman, P

7. A method in accordance with claim 6 and further in- 1958 (Publishedby MacDna1d.and Evans London cluding the step of plating said exposedsurface of nickel England)- Wlth a noble metal WHITMORE A. WILTZ,Primary Examiner.

References Cited by the Examiner v JOHN F. CAMPBELL, Examiner.

UNITED STATES PATENTS P. M. COHEN, Assistant Examiner. 2,793,420 5/1957Johnston et a1 29155.5

2,802,159 8/1957 Stump 317-235

1. A METHOD OF MAKING SEMI-CONDUCTOR DEVICES INCLUDING THE STEPS OFMASKING THE EXPOSED SURFACES OF THE BASE LAYER OF ONE CONDUCTIVITY TYPE,SEPARATING TWO RECTIFYING JUCTIONS, AND THE EXPOSED AREAS, MARGINALLYADJACENT TO SAID RECTIFYING JUNCTIONS, OF THE OPPOSITE CONDUCTIVITYTYPE, TO SAID BASE LAYER, SAID LAYERS BEING IN A SEMICONDUCTOR CRYSTALSLICE, PLATING THE UNMASKED AREAS, AND CUTTING SAID CRYSTAL ACROSS SAIDJUNCTION.
 6. A METHOD OF ESTABLISHING OHMIC CONTACT WITH ASEMICONDUCTING REGION INCLUDING, ELECTROLESS NICKEL PLATING SAIDSEMICONDUCTING REGION IN A PLATING BATH, REMOVING SAID SEMICONDUCTINGREGION FROM SAID PLATING BATH AND IMMEDIATELY INSERTING SAID REGION,WHILE STILL WETTED BY SAID PLATING BATH, INTO A VACUUM FURNACE ANDHEATING FOR A SUFFICIENT LENGTH OF TIME AT 800*C. TO PROVIDE AND EXPOSEDSURFACE OF NICKEL OXIDE AND ELECTROLESS NICKEL PLATING THE LATTERSURFACE TO PROVIDE AN EXPOSED SURFACE OF NICKEL.